The present invention relates to the field of integrated circuits, and in particular to techniques for generating the layout of a circuit block for such an integrated circuit. The circuit block may represent the entire integrated circuit or a component within the integrated circuit.
In the design of semiconductor integrated circuits, it is known to provide automated tools which use a functional design of a planned circuit block (for example in the form of a gate level netlist or a Register Transfer Level representation of the design) and a cell library providing a set of standard cells (the standard cells defining circuit elements, and being “building blocks” for putting together the layout of the circuit block according to the functional design) in order to generate the layout of the circuit block.
Typically, the standard cells are arranged in rows by the automated tool and (considering the rows as running horizontally) the left and right boundaries of each standard cell are such that any given standard cell may be placed next to any other given standard cell. Thus the automated tool typically has free choice in which standard cells are placed where in order to fulfil the requirements of the functional design with a low routing overhead.
Each standard cell in the standard cell library will typically define a corresponding circuit element using transistors. Many types of transistors used in modern systems include a body region, and a known technique to increase the switching speed of such transistors is to apply forward body biasing (FBB) to those transistors. However, whilst this can serve to increase the switching speed of the transistors, it also typically has the side effect of increasing the leakage power of the transistors. Another type of body biasing that can be applied is reverse body biasing (RBB), which can reduce leakage current of the transistor, but has an impact on switching speed.
It would be desirable to improve the benefits derivable from body biasing techniques when designing circuit blocks of an integrated circuit using the earlier-mentioned standard cell approach.